Error updating bootrom

Anyway, i didn't want that someone else go through this also.

The process documented in this article can be used in any Lync 2010 or 2013 environment to setup a centralized provisioning server for managing Polycom SIP phones running Polycom Unified Communications Software (UCS).

This article is not intended to replace or accompany any official Polycom documentation.

---------- ---------- ---------- nvram, .2 bakut , ( ).

BROM_DLL Programdata\SP_FT_Logs Documents and Settings\All Users\Application Data\SP_FT_Logs.

Their is no one telling the exact solution to this problem as this problem is getting common among DZ09 users.

Even i read many of the websites are saying that "Sorry, you can't do anything if you got this problem".

DDR3 Training Sequence - Static MC Init DDR3 Training Sequence - HW Training Procedure DDR3 Training Sequence - Switching XBAR Window to Fast Path Window Boot ROM: Image checksum verification PASSED __ __ _ _ | \/ | __ _ _ ____ _____| | | | |\/| |/ _` | '__\ \ / / _ \ | | | | | | (_| | | \ V / __/ | | |_| |_|\__,_|_| \_/ \___|_|_| _ _ ____ _ | | | | | __ ) ___ ___ | |_ | | | |___| _ \ / _ \ / _ \| __| | |_| |___| |_) | (_) | (_) | |_ \___/ |____/ \___/ \___/ \__| ** LOADER ** U-Boot 2011.12 (Feb 06 2014 - ) Marvell version: v2011.12 2013_Q1.2 Boot version:v1.3.25 Board: RD-AXP-GP rev 1.0 So C: MV78230 B0 running 2 CPUs Custom configuration CPU: Marvell PJ4B (584) v7 (Rev 2) LE CPU 0 CPU @ 1200 [MHz] L2 @ 600 [MHz] TClock @ 250 [MHz] DDR @ 600 [MHz] DDR 32Bit Width, Fast Path Memory Access DDR ECC Disabled DRAM: 256 Mi B Map: Code: 0x0fea7000:0x0ff5e2d4 BSS: 0x0ffefd80 Stack: 0x0f9a6ef8 Heap: 0x0f9a7000:0x0fea7000 NAND: Spansion 1Gb(ID=F101) 128 Mi B MMC: MRVL_MMC: 0 Bad block table found at page 65472, version 0x01 Bad block table found at page 65408, version 0x01 nand_read_bbt: Bad block at 0x000001ca0000 #### auto_recovery #### [u_env] get auto_recovery == yes [u_env] get auto_recovery == yes [u_env] get boot_part == 1 [u_env] get boot_part_ready == 3 auto_recovery enabled:1, boot_part:1, boot_part_ready:3 [boot_count_read] block:0x140000, size:256KB, records:128 [boot_count_read_record] boot_count:2, next_record:42 [boot_count_write] erase:0, auto_recovery-block_offset:0x140000 Updating boot_count ... USB 0: Host Mode USB 1: Host Mode USB 2: Device Mode Modules Detected: mv Eth E6171Switch Basic Init finished Net: mv Sys Neta Init enter set port 0 to rgmii enter set port 1 to rgmii enter egiga0 [PRIME], egiga1 modify Phy Status auto_recovery_check changes bootcmd: run nandboot Hit any key to stop autoboot: 0 NAND read: device 0 offset 0xa00000, size 0x400000 4194304 bytes read: OK ## Booting kernel from Legacy Image at 02000000 ... Total pages: 65024 Kernel command line: console=tty S0,115200 mtdparts=armada-nand:1024K(uboot)ro,256K(u_env),256K(s_env),[email protected](devinfo),[email protected](kernel),[email protected](rootfs),[email protected](alt _kernel),[email protected](alt_rootfs),[email protected](ubifs),[email protected](syscfg) root=/dev/mtdblock5 ro rootfstype=jffs2 init=/sbin/init PID hash table entries: 1024 (order: 0, 4096 bytes) Dentry cache hash table entries: 32768 (order: 5, 131072 bytes) Inode-cache hash table entries: 16384 (order: 4, 65536 bytes) allocated 1048576 bytes of page_cgroup please try 'cgroup_disable=memory' option if you don't want memory cgroups Memory: 256MB = 256MB total Memory: 250768k/250768k available, 11376k reserved, 0K highmem Virtual kernel memory layout: vector : 0xffff0000 - 0xffff1000 ( 4 k B) fixmap : 0xfff00000 - 0xfffe0000 ( 896 k B) vmalloc : 0xd0800000 - 0xfa800000 ( 672 MB) lowmem : 0xc0000000 - 0xd0000000 ( 256 MB) pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB) modules : 0xbf000000 - 0xbfe00000 ( 14 MB) : 0xc0008000 - 0xc06fcf4c (7124 k B) : 0xc06fd000 - 0xc0733b20 ( 219 k B) : 0xc0734000 - 0xc076fb80 ( 239 k B) : 0xc076fba4 - 0xc07c3f28 ( 337 k B) Hierarchical RCU implementation. NR_IRQS:211 Initializing Armada XP SOC Timer 0 sched_clock: 32 bits at 25MHz, resolution 40ns, wraps every 171798ms Calibrating delay loop...

[boot_count_write] offset:0x155000 , length:2048 done PEX 0.0(0): Root Complex Interface, Detected Link X1, GEN 2.0 PEX 0.1(1): Root Complex Interface, Detected Link X1, GEN 1.1 PEX 0.2(2): Root Complex Interface, Detected Link X1, GEN 2.0 PEX 0.3(3): Detected No Link. Image Name: Linux-3.2.40 Created: 2014-06-20 UTC Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 3856032 Bytes = 3.7 Mi B Load Address: 00008000 Entry Point: 00008000 Verifying Checksum ... 1191.11 Bogo MIPS (lpj=5955584) pid_max: default: 32768 minimum: 301 Mount-cache hash table entries: 512 Initializing cgroup subsys debug Initializing cgroup subsys cpuacct Initializing cgroup subsys memory Initializing cgroup subsys devices Initializing cgroup subsys freezer Initializing cgroup subsys blkio CPU: Testing write buffer coherency: ok CPU0: thread -1, cpu 0, socket 0, mpidr 80000000 SMP: prepare CPUs (4 cores) Setting Clocks for secondary CPUs Armada-XP Performance Monitor Unit detected (Marvell ID)!!!

---------- ---------- ---------- trest, DRAM, NAND EMMC.

I shared this information because i also searched for 1 whole day straight and then finally found the solution.

The phones will look for specific firmware files to perform an upgrade/downgrade and will download and upload configuration data in XML files.

Comments are closed.